Sega 32X Handbuch Seite 91
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- Inhaltsverzeichnis
- LESEZEICHEN
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91
Register
0x000001B6: 0xE000 mov #0x00, r0
0x000001B8: 0x2800 mov.b r0, @r8
0x000001BA: 0xD95B mov.l @(0x170, pc), r9 ; 0x00000328, r9 = $FFFFFE92 Cache Control
Register
0x000001BC: 0xE011 mov #0x11, r0
0x000001BE: 0x2900 mov.b r0, @r9 ; Cache Purge, Cache Enabled, 4-way
SDRAMInit:
0x000001C0: 0xD860 mov.l @(0x184, pc), r8 ; 0x00000344, r8 = $26040000
0x000001C2: 0xD95F mov.l @(0x180, pc), r9 ; 0x00000340, r9 = $26000000
0x000001C4: 0xE000 mov #0x00, r0
0x000001C6: 0x2805 mov.w r0, @-r8
0x000001C8: 0x7001 add #0x01, r0
0x000001CA: 0x2805 mov.w r0, @-r8
0x000001CC: 0x7001 add #0x01, r0 ; SDRAM = $0000, $0001, $0002, ...
0x000001CE: 0x2805 mov.w r0, @-r8
0x000001D0: 0x7001 add #0x01, r0
0x000001D2: 0x2805 mov.w r0, @-r8
0x000001D4: 0x7001 add #0x01, r0
0x000001D6: 0x3980 cmp/eq r8, r9
0x000001D8: 0x8BF5 bf 0x000001C6
SDRAMCheck:
0x000001DA: 0xD85A mov.l @(0x16C, pc), r8 ; 0x00000344, r8 = $26040000
0x000001DC: 0xD958 mov.l @(0x164, pc), r9 ; 0x00000340, r9 = $26000000
0x000001DE: 0xE000 mov #0x00, r0
0x000001E0: 0xE102 mov #0x02, r1
0x000001E2: 0xE201 mov #0x01, r2
0x000001E4: 0xD305 mov.l @(0x018, pc), r3 ; 0x000001FC, r3 = $0000FFFF
0x000001E6: 0x3818 sub r1, r8
0x000001E8: 0x6481 mov.w @r8, r4
0x000001EA: 0x2439 and r3, r4
0x000001EC: 0x2039 and r3, r0
0x000001EE: 0x3400 cmp/eq r0, r4
0x000001F0: 0x8B06 bf 0x00000200
0x000001F2: 0x7001 add #0x01, r0
0x000001F4: 0x3980 cmp/eq r8, r9
0x000001F6: 0x8BF6 bf 0x000001E6
0x000001F8: 0xA008 bra 0x0000020C
0x000001FA: 0x0009 nop
org $1FC
dc.l $0000FFFF
SDRAMError:
0x00000200: 0xD001 mov.l @(0x008, pc), r0 ; 0x00000208, r0 = 'SDER'
0x00000202: 0xC208 mov.l r0, @(0x020, gbr) ; Communication Port
0x00000204: 0xAFFC bra 0x00000200
0x00000206: 0x0009 nop
org $208
dc.l $53444552 ; SDER SDRAM Check Error
SDRAMClear:
0x0000020C: 0xD84D mov.l @(0x138, pc), r8 ; 0x00000344, r8 = $26040000
0x0000020E: 0xD94C mov.l @(0x134, pc), r9 ; 0x00000340, r9 = $26000000
0x00000210: 0xE000 mov #0x00, r0
0x00000212: 0x2806 mov.l r0, @-r8
0x00000214: 0x2806 mov.l r0, @-r8
0x00000216: 0x2806 mov.l r0, @-r8
0x00000218: 0x2806 mov.l r0, @-r8
0x0000021A: 0x3980 cmp/eq r8, r9
0x0000021C: 0x8BF9 bf 0x00000212
PWMMaskTest:
0x0000021E: 0xC400 mov.b @(0x000, gbr), r0
0x00000220: 0xC801 tst #0x01, r0
0x00000222: 0x8B59 bf 0x000002D8
0x00000224: 0xDD43 mov.l @(0x110, pc), r13 ; 0x00000334, r13 = $22000400
0x00000226: 0xDC06 mov.l @(0x01C, pc), r12 ; 0x00000240, r12 = $0000036C
- Hardware Manual 1
- Doc. #MAR-32-R4-072294 1
- Terminology 4
- Contents 5
- 1. Introduction to 32X 7
- New Screen Offered 8
- New Sounds Offered 8
- High-Speed Microprocessor 8
- Development Language 8
- 2. Configuration 9
- Figure 2.1 32X Block Diagram 10
- MEGA Drive I/F Component 11
- 32X Cartridge Component 11
- SH2 Component 11
- SDRAM Component 12
- Frame Buffer Component 12
- VDP Component 12
- Color Palette Component 13
- PWM Component 13
- 3. Functions 14
- MEGA Drive Memory Map 15
- ROM Access when using the 32X 16
- Access to the 32X VDP 16
- SH2 Memory Map 17
- Figure 3.2 SH2 Memory Map 17
- Cache Area Access 18
- Cartridge ROM Access 18
- 32X VDP Access 18
- 1.5. Registers 19
- Using the 32X 21
- Interrupt issued for SH2 22
- Switches ROM Cartridge Bank 22
- (Acces : Word) 24
- (Access : Word) 24
- (Acces: Byte/Word) 25
- (Access : Byte/Word) 25
- (Access: Byte/Word) 26
- [SH2 side] 28
- (Access : Byte/Word) 28
- PWM Interrupt Clear Register 30
- (Access : Word) 32
- VDP Registers 36
- 1.6. VDP 39
- Figure 3.4 32X VDP Mapping 41
- Switching Frame Buffers 42
- Figure 3.7 Over Write Image 45
- Line Table Format 47
- Figure 3.8 Line Table Format 47
- Priority 48
- Figure 3.9 Priority 48
- Direct Color Mode 49
- Figure 3.10 Direct Color Mode 49
- Packed Pixel Mode 50
- Figure 3.11 Packed Pixel Mode 50
- Screen Shift Control 51
- Run Length Mode 52
- Figure 3.13 Run Length Mode 52
- FILL Function 53
- Before Fill 53
- After Fill 53
- Mega Drive Master Clock Cycle 54
- 68000 Clock Cycle 54
- SH2 Clock Cycle 54
- VDP Register Latch Timing 56
- 1.7. PWM 57
- Master and Slave 62
- Note 2 : See next page 63
- Figure 3.25 SH2 Address 64
- V: valid bit 64
- Purge (Cache Initialization) 66
- CPU Write 67
- Flow of Data 67
- Master-Slave Communication 68
- Communication Port 69
- CMD Interrupt 69
- 4. 32X Block Access 72
- SH2 Address Space 73
- Cache-through Access 74
- VDP Access Competition 74
- ROM Access Competition 74
- Competition with other CPUs 76
- Frame Buffer Access 76
- 32X Mode and Cartridge ROM 77
- Frame Buffer 77
- VDP Register 78
- System Register 78
- Boot ROM 78
- SDRAM Access Time 78
- 5. Other 79
- Initial Program 83
- Security 83
- 6. Annexes 88
- 1.16. Master Boot ROM 89
- 1.17. Initial program 95
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