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Cache Area Access

Cache memory is memory used for rapidly supplying commands, operans, and data to the

CPU. The 32X accesses the cache after commands and data are loaded in the SDRAM. In

32X, after having loaded command and data into the SDRAM, the cache access is

performed. The 32X system register and VDP register, among others, must be cache-

through accessed because values through the VDP or other CPU are replaced and the

contents of the cache can no longer be guaranteed.

Cartridge ROM Access

Only when the RV (ROM to VRAM DMA) bit is 0 can SH2 be accessed to the cartirdge

ROM. When the RV bit is 1 and if accessing from SH2 to the cartridge ROM, a wait

occurs until 68000 replaces the TV bit with 0. The RV bit from SH2 can only read.

32X VDP Access

Only when the FM (VDP access authorization) bit is 1 can the frame buffer overwrite

images, VDP register, and color palette access from the SH22 side. When the FM bit is 0,

read is undefined and write is ignored. The color palette can access only in words but not

in bytes.

The frame buffer and overwrite image have 4 word write FIFO and can write in 3 clock

cycles. Five clock cycle are required when continuously writing 4 words or more.

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Sega 32X Handbuch Seite 18