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DMA

SH2 contains a 2 channel DMA. If transfer request is set to auto request and is within the

SH2 address space, transfer betwwen memories can be performed (at generation inside

the DMA).

When transfert request is done by an external request (DREQ), DMA transfer can be done

by the dual address mode for :

- channel 0 from FIFO to SH2-side RAM;

- channel 1 PWM sound source pulse width register.

DMA transfer can be done by the dual address mode. External requests should be used by

the edge trigger, not the level trigger.

Figure 3.27 DMA between MEGA Drive and 32X

DMA transfer from the MEGA Drive to 32X is done through the FIFO packaged 32X. If

data is set to this FIFO from the MEGA Drive, transfer request (DREQ0) occurs for the

DMA of SH2. In the SH2 side, DMA channel 0 is set in externalrequest and FIFO is

specified and transferred to the source address.

This sets data tot FIFO from the MEGA Drive side.

CPU Write is the method for writing to FIFO by 68000 directly for each word. At a time,

if the Full bit of the DREQ control register is 0 write is possible and if Full bit is 1 then it

is FIFO Full.

68000

FIFO

SH2

DMA

SDRAM

DRAM

CPU Write

DREQ0

Flow of Data

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Sega 32X Handbuch Seite 67