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Sega 32X Handbuch Seite 63

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63
Cache
SH2 contains 4-Kbyte cache memory. Since this memory is accessed per 1 cycle, it is
effectively executed by reducing the wait states during access to external chips, such as
SDRAM, and minimizing command execution pipeline perturbation.
Cache Specifications
- 4-Kbyte, command/data mixed type
- 64 entries x 4-way associative, 16-byte line length (selection of 64 entries x 2 ways
+ 2-kbyte RAM)
- Data write is write-through type, LRU repress algorithm
- able to select command only / data only repress.
0000 0000h
CS0 space cache area
0200 0000h
CS1 space cache area
0400 0000h
CS2 space cache area
0600 0000h
CS3 space cache area
Address upper 3 bits
1
= "000" space
Used when accessing CS0~3 through cache (Sets
control register CCR CE bit to 1)
0800 0000h
Reserve
2000 0000h
CS0 space cache through area
2200 0000h
CS1 space cache through area
2400 0000h
CS2 space cache through area
2600 0000h
CS3 space cache through area
Address upper 3 bits = "001" space
Used when accessing CS0~3 not through cache
2800 0000h
Reserve
4000 0000h
Associative purge
Address upper 3 bits = "010" space
Used in purge of specific line of cache
6000 0000h
Address array read/write space
Address upper 3 bits = "011" space
Used when directly accessing address array
2
of
cache
8000 0000h
Reserve
C000 0000h
Data array read/write space
Address upper 3 bits = "110" space
Used when directly accessing data array
2
of cache
C000 1000h
(Occupied by shadow space)
E000 1000h
(Occupied by shadow space)
FFFF 8000h
Built-in I/O module
Address upper 3 bits = "111" space
Access through cache not possible
FFFF FFFFh
Note 1 : Specific address of access space
Note 2 : See next page
Figure 3.24 Relationship of SH2 Address Space and Cache
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