23
Transfers Data to SH2 DMAC
Transfers Data to SH2 DMAC
(Access : Byte/Word)
Ful: DMA FIFO Full
0: Can write
1: Cannot write
RV: ROM to VRAM DMA
0: NO OPERATION (initial value)
1: DMA Start Allowed
The SH2 side cannot access the ROM when RV = 1 (when doing ROM to VRAM DMA,
be sure that RV = 1). Waits until value becomes 0 (RV = 0) before accessing.
CPU Write (68K writes data in FIFO)
The internal system starts operation when 68S is 1. writing 0 force-ends the operation. It
is automatically set to 0 after DMA ends.
68K to SH DREQ Source Address Register
(Acces : Word)
Because the DREQ circuit does not use this data, nothing needs to be set ath the time of
CPU WRITE.
Kommentare zu diesen Handbüchern